1. Field of the Invention
This invention relates to a semiconductor device, more specifically an increased integration level of the semiconductor memory device.
2. Description of the Related Art
A conventional nonvolatile memory is described with reference to FIG. 7A, 7B and FIG. 8 hereinbelow. FIG. 7A shows a plan view of the nonvolatile memory 35. Also, FIG. 7B is a cross-sectional view of a line VIIB--VIIB of the nonvolatile memory 35 shown in FIG. 7A. The nonvolatile memory 35 having a plurality of memory elements 35a, 35b which carry out data-storage and data-erase by injecting electrons to a floating gate electrode 11 and pull out the electrons therefrom as shown in FIG. 7B. A source region of each element is formed extendedly as in a column as one region as shown in FIG. 7A and FIG. 7B. FIG. 8 is a cross-sectional view of a line VIII--VIII of the nonvolatile memory 35 shown in FIG. 7A.
The field oxidation layers 19 are isolated regions as shown in the figures. The floating gate electrode 11 is formed partially on the field oxidation layers 19. Also, control gate electrodes 12 are formed as word lines extendedly in a column as one electrode on the field oxidation layers 19.
The source region is formed by carrying out ion implantation by utilizing the control gate electrodes 12 as a mask in the nonvolatile memory 35. As a result, the source region can not be formed under the field oxidation layers 19 because implanted ions can not reach to the field oxidation layer 19. Consequently, it is necessary to maintain a certain distance (a distance .beta.2) between the control gates located adjacently in order to form the word lines properly (see FIG. 8).
Further, an additional distance .beta.1 is required between the control gates located adjacently as a margin in consideration of mis-alignment of the mask. That is, the width of the source region 4 is narrowed for a certain width when the control gate electrode 12 is formed out of a predetermined position. In order to avoid such a case, a certain width of margin for the narrowed width expected is required.
In addition, a passivation layer which covers the surface is formed unevenly with steps when the distance between the adjacent control gates becomes large as described above. As a result, there is slight probability of disconnection of wiring when a wiring layer is formed on the passivation layer.